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UserspaceEmulator: Fix broken inline assembly for asymmetric op_foos

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When the Destination and Source of an op_foo were types of different
sizes, the generated assembly was not filling up the "source" register
fully in some cases. This led to incorrect results.
This commit is contained in:
Andreas Kling
2020-07-11 17:03:42 +02:00
parent c4ec38ddb5
commit 0a448ee960
1 changed files with 9 additions and 9 deletions
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18
DevTools/UserspaceEmulator/SoftCPU.cpp
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@@ -166,15 +166,15 @@ static typename TypeDoubler<Destination>::type op_xor(SoftCPU& cpu, const Destin
if constexpr (sizeof(Destination) == 4) {
asm volatile("xorl %%ecx, %%eax\n"
: "=a"(result)
: "a"(dest), "c"(src));
: "a"(dest), "c"((u32)src));
} else if constexpr (sizeof(Destination) == 2) {
asm volatile("xor %%cx, %%ax\n"
: "=a"(result)
: "a"(dest), "c"(src));
: "a"(dest), "c"((u16)src));
} else if constexpr (sizeof(Destination) == 1) {
asm volatile("xorb %%cl, %%al\n"
: "=a"(result)
: "a"(dest), "c"(src));
: "a"(dest), "c"((u8)src));
} else {
ASSERT_NOT_REACHED();
}
@@ -197,15 +197,15 @@ static typename TypeDoubler<Destination>::type op_sub(SoftCPU& cpu, const Destin
if constexpr (sizeof(Destination) == 4) {
asm volatile("subl %%ecx, %%eax\n"
: "=a"(result)
: "a"(dest), "c"(src));
: "a"(dest), "c"((u32)src));
} else if constexpr (sizeof(Destination) == 2) {
asm volatile("subw %%cx, %%ax\n"
: "=a"(result)
: "a"(dest), "c"(src));
: "a"(dest), "c"((u16)src));
} else if constexpr (sizeof(Destination) == 1) {
asm volatile("subb %%cl, %%al\n"
: "=a"(result)
: "a"(dest), "c"(src));
: "a"(dest), "c"((u8)src));
} else {
ASSERT_NOT_REACHED();
}
@@ -228,15 +228,15 @@ static Destination op_add(SoftCPU& cpu, Destination& dest, const Source& src)
if constexpr (sizeof(Destination) == 4) {
asm volatile("addl %%ecx, %%eax\n"
: "=a"(result)
: "a"(dest), "c"(src));
: "a"(dest), "c"((u32)src));
} else if constexpr (sizeof(Destination) == 2) {
asm volatile("addw %%cx, %%ax\n"
: "=a"(result)
: "a"(dest), "c"(src));
: "a"(dest), "c"((u16)src));
} else if constexpr (sizeof(Destination) == 1) {
asm volatile("addb %%cl, %%al\n"
: "=a"(result)
: "a"(dest), "c"(src));
: "a"(dest), "c"((u8)src));
} else {
ASSERT_NOT_REACHED();
}