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LibX86: Disassemble most FPU instructions starting with D9

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Some of these don't just use the REG bits of the mod/rm byte
as slashes, but also the R/M bits to have up to 9 different
instructions per opcode/slash combination (1 opcode requires
that MOD is != 11, the other 8 have MODE == 11).

This is done by making the slashes table two levels deep for
these cases.

Some of this is cosmetic (e.g "FST st0" has no effect already,
but its bit pattern gets disassembled as "FNOP"), but for
most uses it isn't.

FSTENV and FSTCW have an extraordinary 0x9b prefix. This is
not yet handled in this patch.
This commit is contained in:
Nico Weber
2020-07-28 11:09:54 -04:00
committed by Andreas Kling
parent 6f12ab3ced
commit c99a3efc5b
5 changed files with 209 additions and 13 deletions
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36
DevTools/UserspaceEmulator/SoftCPU.cpp
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@@ -1379,6 +1379,42 @@ void SoftCPU::FSUB_RM32(const X86::Instruction&) { TODO(); }
void SoftCPU::FSUBR_RM32(const X86::Instruction&) { TODO(); }
void SoftCPU::FDIV_RM32(const X86::Instruction&) { TODO(); }
void SoftCPU::FDIVR_RM32(const X86::Instruction&) { TODO(); }
void SoftCPU::FLD_RM32(const X86::Instruction&) { TODO(); }
void SoftCPU::FXCH(const X86::Instruction&) { TODO(); }
void SoftCPU::FST_RM32(const X86::Instruction&) { TODO(); }
void SoftCPU::FNOP(const X86::Instruction&) { TODO(); }
void SoftCPU::FSTP_RM32(const X86::Instruction&) { TODO(); }
void SoftCPU::FLDENV(const X86::Instruction&) { TODO(); }
void SoftCPU::FCHS(const X86::Instruction&) { TODO(); }
void SoftCPU::FABS(const X86::Instruction&) { TODO(); }
void SoftCPU::FTST(const X86::Instruction&) { TODO(); }
void SoftCPU::FXAM(const X86::Instruction&) { TODO(); }
void SoftCPU::FLDCW(const X86::Instruction&) { TODO(); }
void SoftCPU::FLD1(const X86::Instruction&) { TODO(); }
void SoftCPU::FLDL2T(const X86::Instruction&) { TODO(); }
void SoftCPU::FLDL2E(const X86::Instruction&) { TODO(); }
void SoftCPU::FLDPI(const X86::Instruction&) { TODO(); }
void SoftCPU::FLDLG2(const X86::Instruction&) { TODO(); }
void SoftCPU::FLDLN2(const X86::Instruction&) { TODO(); }
void SoftCPU::FLDZ(const X86::Instruction&) { TODO(); }
void SoftCPU::FNSTENV(const X86::Instruction&) { TODO(); }
void SoftCPU::F2XM1(const X86::Instruction&) { TODO(); };
void SoftCPU::FYL2X(const X86::Instruction&) { TODO(); };
void SoftCPU::FPTAN(const X86::Instruction&) { TODO(); };
void SoftCPU::FPATAN(const X86::Instruction&) { TODO(); };
void SoftCPU::FXTRACT(const X86::Instruction&) { TODO(); };
void SoftCPU::FPREM1(const X86::Instruction&) { TODO(); };
void SoftCPU::FDECSTP(const X86::Instruction&) { TODO(); };
void SoftCPU::FINCSTP(const X86::Instruction&) { TODO(); };
void SoftCPU::FNSTCW(const X86::Instruction&) { TODO(); };
void SoftCPU::FPREM(const X86::Instruction&) { TODO(); };
void SoftCPU::FYL2XP1(const X86::Instruction&) { TODO(); };
void SoftCPU::FSQRT(const X86::Instruction&) { TODO(); };
void SoftCPU::FSINCOS(const X86::Instruction&) { TODO(); };
void SoftCPU::FRNDINT(const X86::Instruction&) { TODO(); };
void SoftCPU::FSCALE(const X86::Instruction&) { TODO(); };
void SoftCPU::FSIN(const X86::Instruction&) { TODO(); };
void SoftCPU::FCOS(const X86::Instruction&) { TODO(); };
void SoftCPU::FADD_RM64(const X86::Instruction&) { TODO(); }
void SoftCPU::FMUL_RM64(const X86::Instruction&) { TODO(); }
void SoftCPU::FCOM_RM64(const X86::Instruction&) { TODO(); }