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https://github.com/fergalmoran/ladybird.git
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247109cee6
Until now the kernel was always executing with SP_EL0, as this made the initial dropping to EL1 a bit easier. This commit changes this behaviour to use the corresponding SP_ELx for each exception level. To make sure that the execution of the C++ code can continue, the current stack pointer is copied into the corresponding SP_ELx just before dropping an exception level.
131 lines
4.6 KiB
C++
131 lines
4.6 KiB
C++
/*
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* Copyright (c) 2021, James Mintram <me@jamesrm.com>
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*
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* SPDX-License-Identifier: BSD-2-Clause
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*/
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#include <Kernel/Arch/aarch64/ASM_wrapper.h>
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#include <Kernel/Arch/aarch64/CPU.h>
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#include <Kernel/Arch/aarch64/Processor.h>
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#include <Kernel/Arch/aarch64/Registers.h>
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#include <Kernel/Panic.h>
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extern "C" uintptr_t vector_table_el1;
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namespace Kernel {
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static void drop_el3_to_el2()
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{
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Aarch64::SCR_EL3 secure_configuration_register_el3 = {};
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secure_configuration_register_el3.ST = 1; // Don't trap access to Counter-timer Physical Secure registers
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secure_configuration_register_el3.RW = 1; // Lower level to use Aarch64
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secure_configuration_register_el3.NS = 1; // Non-secure state
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secure_configuration_register_el3.HCE = 1; // Enable Hypervisor instructions at all levels
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Aarch64::SCR_EL3::write(secure_configuration_register_el3);
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Aarch64::SPSR_EL3 saved_program_status_register_el3 = {};
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// Mask (disable) all interrupts
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saved_program_status_register_el3.A = 1;
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saved_program_status_register_el3.I = 1;
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saved_program_status_register_el3.F = 1;
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saved_program_status_register_el3.D = 1;
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// Indicate EL1 as exception origin mode (so we go back there)
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saved_program_status_register_el3.M = Aarch64::SPSR_EL3::Mode::EL2h;
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// Set the register
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Aarch64::SPSR_EL3::write(saved_program_status_register_el3);
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// This will jump into os_start() below
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Aarch64::Asm::enter_el2_from_el3();
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}
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static void drop_el2_to_el1()
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{
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Aarch64::HCR_EL2 hypervisor_configuration_register_el2 = {};
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hypervisor_configuration_register_el2.RW = 1; // EL1 to use 64-bit mode
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Aarch64::HCR_EL2::write(hypervisor_configuration_register_el2);
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Aarch64::SPSR_EL2 saved_program_status_register_el2 = {};
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// Mask (disable) all interrupts
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saved_program_status_register_el2.A = 1;
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saved_program_status_register_el2.I = 1;
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saved_program_status_register_el2.F = 1;
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// Indicate EL1 as exception origin mode (so we go back there)
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saved_program_status_register_el2.M = Aarch64::SPSR_EL2::Mode::EL1h;
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Aarch64::SPSR_EL2::write(saved_program_status_register_el2);
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Aarch64::Asm::enter_el1_from_el2();
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}
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static void setup_el1()
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{
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Aarch64::SCTLR_EL1 system_control_register_el1 = Aarch64::SCTLR_EL1::reset_value();
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system_control_register_el1.UCT = 1; // Don't trap access to CTR_EL0
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system_control_register_el1.nTWE = 1; // Don't trap WFE instructions
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system_control_register_el1.nTWI = 1; // Don't trap WFI instructions
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system_control_register_el1.DZE = 1; // Don't trap DC ZVA instructions
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system_control_register_el1.UMA = 1; // Don't trap access to DAIF (debugging) flags of EFLAGS register
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system_control_register_el1.SA0 = 1; // Enable stack access alignment check for EL0
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system_control_register_el1.SA = 1; // Enable stack access alignment check for EL1
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system_control_register_el1.A = 1; // Enable memory access alignment check
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Aarch64::SCTLR_EL1::write(system_control_register_el1);
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Aarch64::Asm::load_el1_vector_table(&vector_table_el1);
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}
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void initialize_exceptions()
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{
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auto base_exception_level = Aarch64::Asm::get_current_exception_level();
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if (base_exception_level > Aarch64::Asm::ExceptionLevel::EL3) {
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panic_without_mmu("Started in unknown EL (Greater than EL3)"sv);
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} else if (base_exception_level < Aarch64::Asm::ExceptionLevel::EL1) {
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panic_without_mmu("Started in unsupported EL (Less than EL1)"sv);
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} else {
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if (base_exception_level == Aarch64::Asm::ExceptionLevel::EL1)
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dbgln_without_mmu("Started in EL1"sv);
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else if (base_exception_level == Aarch64::Asm::ExceptionLevel::EL2)
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dbgln_without_mmu("Started in EL2"sv);
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else if (base_exception_level == Aarch64::Asm::ExceptionLevel::EL3)
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dbgln_without_mmu("Started in EL3"sv);
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}
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if (base_exception_level > Aarch64::Asm::ExceptionLevel::EL2) {
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drop_el3_to_el2();
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dbgln_without_mmu("Dropped to EL2"sv);
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}
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if (base_exception_level > Aarch64::Asm::ExceptionLevel::EL1) {
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drop_el2_to_el1();
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dbgln_without_mmu("Dropped to EL1"sv);
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}
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setup_el1();
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dbgln_without_mmu("Set up EL1"sv);
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}
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// NOTE: The normal PANIC macro cannot be used early in the boot process when the MMU is disabled,
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// as it will access global variables, which will cause a crash since they aren't mapped yet.
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void panic_without_mmu(StringView message)
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{
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(void)message;
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// FIXME: Print out message to early boot console.
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Processor::halt();
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}
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void dbgln_without_mmu(StringView message)
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{
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(void)message;
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// FIXME: Print out message to early boot console.
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}
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}
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