mirror of
https://github.com/fergalmoran/ladybird.git
synced 2026-01-04 07:36:50 +00:00
375d269b21
It seems that not setting the framelist address register was causing the entire system to lock up as it generated an insane interrupt storm in the IRQ handler for the UHCI controller. We now allocate a 4KiB aligned page via `MemoryManager::allocate_supervisor_physical_page()` and set every value to 1. In effect, this creates a framelist with each entry being a "TERMINATE" entry in which the controller stalls until its' 1mS time slice is up. Some more registers have also been set for consistency, though it seems like this don't need to be set explicitly in software.
140 lines
4.9 KiB
C++
140 lines
4.9 KiB
C++
/*
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* Copyright (c) 2020, Andreas Kling <kling@serenityos.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <Kernel/Devices/USB/UHCIController.h>
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#include <Kernel/StdLib.h>
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#include <Kernel/VM/MemoryManager.h>
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#define UHCI_ENABLED 1
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namespace Kernel::USB {
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static constexpr u16 UHCI_USBCMD_RUN = 0x0001;
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static constexpr u16 UHCI_USBCMD_HOST_CONTROLLER_RESET = 0x0002;
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static constexpr u16 UHCI_USBCMD_GLOBAL_RESET = 0x0004;
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static constexpr u16 UHCI_USBCMD_ENTER_GLOBAL_SUSPEND_MODE = 0x0008;
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static constexpr u16 UHCI_USBCMD_FORCE_GLOBAL_RESUME = 0x0010;
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static constexpr u16 UHCI_USBCMD_SOFTWARE_DEBUG = 0x0020;
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static constexpr u16 UHCI_USBCMD_CONFIGURE_FLAG = 0x0040;
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static constexpr u16 UHCI_USBCMD_MAX_PACKET = 0x0080;
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static constexpr u16 UHCI_USBSTS_HOST_CONTROLLER_HALTED = 0x0020;
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static constexpr u16 UHCI_USBSTS_HOST_CONTROLLER_PROCESS_ERROR = 0x0010;
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static constexpr u16 UHCI_USBSTS_PCI_BUS_ERROR = 0x0008;
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static constexpr u16 UHCI_USBSTS_RESUME_RECEIVED = 0x0004;
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static constexpr u16 UHCI_USBSTS_USB_ERROR_INTERRUPT = 0x0002;
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static constexpr u16 UHCI_USBSTS_USB_INTERRUPT = 0x0001;
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static constexpr u8 UHCI_USBINTR_TIMEOUT_CRC_ENABLE = 0x01;
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static constexpr u8 UHCI_USBINTR_RESUME_INTR_ENABLE = 0x02;
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static constexpr u8 UHCI_USBINTR_IOC_ENABLE = 0x04;
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static constexpr u8 UHCI_USBINTR_SHORT_PACKET_INTR_ENABLE = 0x08;
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void UHCIController::detect()
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{
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#if !UHCI_ENABLED
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return;
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#endif
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PCI::enumerate([&](const PCI::Address& address, PCI::ID id) {
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if (address.is_null())
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return;
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if (PCI::get_class(address) == 0xc && PCI::get_subclass(address) == 0x03 && PCI::get_programming_interface(address) == 0) {
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new UHCIController(address, id);
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}
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});
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}
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UHCIController::UHCIController(PCI::Address address, PCI::ID id)
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: PCI::Device(address)
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, m_io_base(PCI::get_BAR4(pci_address()) & ~1)
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{
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klog() << "UHCI: Controller found " << id << " @ " << address;
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klog() << "UHCI: I/O base " << m_io_base;
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klog() << "UHCI: Interrupt line: " << PCI::get_interrupt_line(pci_address());
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reset();
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start();
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}
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UHCIController::~UHCIController()
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{
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}
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void UHCIController::reset()
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{
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stop();
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write_usbcmd(UHCI_USBCMD_HOST_CONTROLLER_RESET);
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// FIXME: Timeout
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for (;;) {
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if (read_usbcmd() & UHCI_USBCMD_HOST_CONTROLLER_RESET)
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continue;
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break;
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}
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// Let's allocate the physical page for the Frame List (which is 4KiB aligned)
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m_framelist = MemoryManager::the().allocate_supervisor_physical_page()->paddr();
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klog() << "UHCI: Allocated framelist at physical address " << m_framelist;
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memset(reinterpret_cast<u32*>(low_physical_to_virtual(m_framelist.as_ptr())), 1, 1024); // All frames are TERMINATE frames
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write_sofmod(64); // 1mS frame time
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write_flbaseadd(m_framelist.get()); // Frame list (physical) address
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write_frnum(0); // Set the initial frame number
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// Enable all interrupt types
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write_frnum(UHCI_USBINTR_TIMEOUT_CRC_ENABLE | UHCI_USBINTR_RESUME_INTR_ENABLE | UHCI_USBINTR_IOC_ENABLE | UHCI_USBINTR_SHORT_PACKET_INTR_ENABLE);
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klog() << "UHCI: Reset completed!";
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}
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void UHCIController::stop()
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{
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write_usbcmd(read_usbcmd() & ~UHCI_USBCMD_RUN);
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// FIXME: Timeout
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for (;;) {
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if (read_usbsts() & UHCI_USBSTS_HOST_CONTROLLER_HALTED)
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break;
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}
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}
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void UHCIController::start()
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{
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write_usbcmd(read_usbcmd() | UHCI_USBCMD_RUN);
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// FIXME: Timeout
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for (;;) {
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if (!(read_usbsts() & UHCI_USBSTS_HOST_CONTROLLER_HALTED))
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break;
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}
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klog() << "UHCI: Started!";
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}
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void UHCIController::handle_irq(const RegisterState&)
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{
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}
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}
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