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https://github.com/fergalmoran/ladybird.git
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827322c139
As MMIO is placed at fixed physical addressed, and does not need to be backed by real RAM physical pages, there's no need to use PhysicalPage instances to track their pages. This results in slightly reduced allocations, but more importantly makes MMIO addresses which end up after the normal RAM ranges work, like 64-bit PCI BARs usually are.
84 lines
3.7 KiB
C++
84 lines
3.7 KiB
C++
/*
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* Copyright (c) 2023, Leon Albrecht <leon.a@serenityos.org>
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*
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* SPDX-License-Identifier: BSD-2-Clause
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*/
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#include <Kernel/Bus/PCI/API.h>
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#include <Kernel/Bus/PCI/BarMapping.h>
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#include <Kernel/Bus/USB/EHCI/EHCIController.h>
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namespace Kernel::USB::EHCI {
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ErrorOr<NonnullLockRefPtr<EHCIController>> EHCIController::try_to_initialize(const PCI::DeviceIdentifier& pci_device_identifier)
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{
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// FIXME: This assumes the BIOS left us a physical region for the controller
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auto pci_bar_address = TRY(PCI::get_bar_address(pci_device_identifier, SpaceBaseAddressRegister));
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auto pci_bar_space_size = PCI::get_BAR_space_size(pci_device_identifier, SpaceBaseAddressRegister);
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auto register_region_size = TRY(Memory::page_round_up(pci_bar_address.offset_in_page() + pci_bar_space_size));
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auto register_region = TRY(MM.allocate_mmio_kernel_region(pci_bar_address.page_base(), register_region_size, {}, Memory::Region::Access::ReadWrite));
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VirtualAddress register_base_address = register_region->vaddr().offset(pci_bar_address.offset_in_page());
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PCI::enable_bus_mastering(pci_device_identifier);
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PCI::enable_memory_space(pci_device_identifier);
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auto controller = TRY(adopt_nonnull_lock_ref_or_enomem(new (nothrow) EHCIController(pci_device_identifier, move(register_region), register_base_address)));
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TRY(controller->initialize());
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return controller;
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}
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EHCIController::EHCIController(PCI::DeviceIdentifier const& pci_device_identifier, NonnullOwnPtr<Memory::Region> register_region, VirtualAddress register_base_address)
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: PCI::Device(pci_device_identifier)
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, m_register_region(move(register_region))
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{
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m_cap_regs = bit_cast<CapabilityRegisters const*>(register_base_address.get());
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m_op_regs = bit_cast<OperationalRegisters volatile*>(register_base_address.get() + m_cap_regs->capability_length);
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}
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ErrorOr<void> EHCIController::initialize()
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{
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dmesgln_pci(*this, "Controller found {} @ {}", PCI::get_hardware_id(device_identifier()), device_identifier().address());
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dmesgln_pci(*this, "Version {}.{}", m_cap_regs->interface_version.major, m_cap_regs->interface_version.minor);
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u8 n_ports = m_cap_regs->structural_parameters.n_ports;
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dmesgln_pci(*this, "NPorts: {}", n_ports);
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u8 n_cc = m_cap_regs->structural_parameters.n_companion_controllers;
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u8 n_pcc = m_cap_regs->structural_parameters.n_ports_per_companion_controller;
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dmesgln_pci(*this, "Companion Controllers: {}", n_cc);
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dmesgln_pci(*this, "Ports per Companion Controllers: {}", n_pcc);
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if (n_ports > n_cc * n_pcc) {
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dmesgln_pci(*this, "Warning: Not all ports of the EHCI controller are addressable via companion controllers");
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dmesgln_pci(*this, " Some USB 2.0 ports might not be functional");
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}
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u8 EECP = m_cap_regs->capability_parameters.ehci_extended_capabilities_pointer;
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if (EECP) {
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SpinlockLocker locker(device_identifier().operation_lock());
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auto legacy_support = bit_cast<LegacySupport>(PCI::read32_locked(device_identifier(), PCI::RegisterOffset { EECP }));
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if (legacy_support.HC_BIOS_owned_semaphore)
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dmesgln_pci(*this, "Warning: EHCI controller is BIOS owned");
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}
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// FIXME: Decide which Interrupts we want
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// FIXME: Detect and switch on 64 bit support
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// FIXME: Allocate and initialize Task Lists
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// * Synchronous
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// * Asynchronous
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// * Leave space for for the actual list items
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// and IO scratch space in case we cannot use the buffer from the request
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// FIXME: Initialize the controller and start it
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// * Setup the root hub emulation
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// * Enable Software routing (CF)
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// * Maybe configure port power
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return {};
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}
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}
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