Linus Groh 20e2e39fcc Kernel: Expose size of L1 data/instruction, L2, and L3 CPU caches :^) ...

These are added as properties of the "caches" object to each processor,
if available.

2022-05-29 15:23:57 +02:00

..

aarch64

Kernel: Report value of ESR_EL1 when exception happens on aarch64

2022-05-21 20:23:32 +01:00

x86

Kernel: Expose size of L1 data/instruction, L2, and L3 CPU caches :^)

2022-05-29 15:23:57 +02:00

CPU.h

Kernel: Make handle_crash available to aarch64

2022-04-02 19:34:20 -07:00

DeferredCallEntry.h

Kernel: Extract DeferredCallEntry from Arch/Processor.h

2021-12-11 13:23:27 -08:00

mcontext.h

Kernel: Create a stub mcontext for aarch64

2022-03-12 14:54:12 -08:00

PageDirectory.h

Kernel: Make PageDirectory.cpp compile on aarch64

2022-04-02 19:34:20 -07:00

PageFault.h

Kernel: Make PageDirectory.cpp compile on aarch64

2022-04-02 19:34:20 -07:00

Processor.h

Everywhere: Run clang-format

2022-04-01 21:24:45 +01:00

ProcessorSpecificDataID.h

Kernel: Extract ProcessorSpecificDataID from from Arch/Processor.h

2021-12-11 13:23:27 -08:00

RegisterState.h

…

SafeMem.h

Kernel: Move Kernel/Arch/x86/SafeMem.h to Kernel/Arch/SafeMem.h

2022-05-03 21:53:36 +02:00

ScopedCritical.h

…

SmapDisabler.h

…

Spinlock.h

Kernel: Move Arch/x86/Spinlock.h and add stubs for aarch64

2022-05-03 21:53:36 +02:00