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040e0fe88c
This simple delay loop uses the time CSR to wait for the given amount of time. The tick frequency of the CSR is read from the /cpus/timebase-frequency devicetree property.
34 lines
843 B
C++
34 lines
843 B
C++
/*
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* Copyright (c) 2023, Sönke Holz <sholz8530@gmail.com>
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*
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* SPDX-License-Identifier: BSD-2-Clause
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*/
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#include <AK/Assertions.h>
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#include <Kernel/Arch/Processor.h>
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#include <Kernel/Arch/riscv64/CPU.h>
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#include <Kernel/Arch/riscv64/CSR.h>
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#include <Kernel/Arch/riscv64/Delay.h>
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namespace Kernel {
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static u32 s_timebase_frequency = 0;
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void microseconds_delay(u32 microseconds)
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{
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VERIFY(s_timebase_frequency != 0);
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u64 const start = RISCV64::CSR::read(RISCV64::CSR::Address::TIME);
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u64 const delta = (static_cast<u64>(microseconds) * s_timebase_frequency) / 1'000'000ull;
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while ((RISCV64::CSR::read(RISCV64::CSR::Address::TIME) - start) < delta)
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Processor::pause();
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}
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void init_delay_loop()
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{
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s_timebase_frequency = DeviceTree::get().resolve_property("/cpus/timebase-frequency"sv).value().as<u32>();
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}
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}
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