mirror of
https://github.com/fergalmoran/ladybird.git
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de02a2680f
This means that userspace breakpoint traps no longer panic the kernel. This also causes us to no longer panic on failed assertions in userspace when using gcc, as gcc compiles __builtin_trap to breakpoint instructions on RISC-V.
254 lines
10 KiB
C++
254 lines
10 KiB
C++
/*
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* Copyright (c) 2023, Sönke Holz <sholz8530@gmail.com>
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*
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* SPDX-License-Identifier: BSD-2-Clause
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*/
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#include <AK/Error.h>
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#include <AK/Types.h>
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#include <Kernel/API/POSIX/signal_numbers.h>
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#include <Kernel/Arch/CPU.h>
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#include <Kernel/Arch/Interrupts.h>
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#include <Kernel/Arch/PageFault.h>
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#include <Kernel/Arch/TrapFrame.h>
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#include <Kernel/Arch/riscv64/InterruptManagement.h>
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#include <Kernel/Arch/riscv64/Timer.h>
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#include <Kernel/Interrupts/GenericInterruptHandler.h>
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#include <Kernel/Interrupts/SharedIRQHandler.h>
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#include <Kernel/Interrupts/UnhandledInterruptHandler.h>
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#include <Kernel/Library/StdLib.h>
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#include <Kernel/Tasks/Process.h>
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#include <Kernel/Tasks/Thread.h>
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#include <Kernel/Tasks/ThreadTracer.h>
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namespace Kernel {
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extern "C" void syscall_handler(TrapFrame const*);
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// FIXME: Share this array with x86_64/aarch64 somehow and consider if this really needs to use raw pointers and not OwnPtrs
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static Array<GenericInterruptHandler*, 256> s_interrupt_handlers;
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void dump_registers(RegisterState const& regs)
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{
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dbgln("scause: {} ({:p})", regs.scause, to_underlying(regs.scause));
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dbgln("sepc: {:p}", regs.sepc);
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dbgln("stval: {:p}", regs.stval);
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dbgln("sstatus: {}", regs.sstatus);
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dbgln("ra={:p} sp={:p} gp={:p} tp={:p} fp={:p}", regs.x[0], regs.x[1], regs.x[2], regs.x[3], regs.x[7]);
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dbgln("a0={:p} a1={:p} a2={:p} a3={:p} a4={:p} a5={:p} a6={:p} a7={:p}", regs.x[9], regs.x[10], regs.x[11], regs.x[12], regs.x[13], regs.x[14], regs.x[15], regs.x[16]);
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dbgln("t0={:p} t1={:p} t2={:p} t3={:p} t4={:p} t5={:p} t6={:p}", regs.x[4], regs.x[5], regs.x[6], regs.x[27], regs.x[28], regs.x[29], regs.x[30]);
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dbgln("s1={:p} s2={:p} s3={:p} s4={:p} s5={:p} s6={:p} s7={:p} s8={:p} s9={:p} s10={:p} s11={:p}", regs.x[8], regs.x[17], regs.x[18], regs.x[19], regs.x[20], regs.x[21], regs.x[22], regs.x[23], regs.x[24], regs.x[25], regs.x[26]);
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}
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extern "C" void trap_handler(TrapFrame& trap_frame);
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extern "C" void trap_handler(TrapFrame& trap_frame)
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{
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auto scause = trap_frame.regs->scause;
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// We have to increment sepc for these exceptions, as we otherwise would return to the instruction causing the trap.
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// sepc has to be incremented before interrupts are re-enabled, as code triggered by interrupts also can cause sepc to be updated.
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if (scause == RISCV64::CSR::SCAUSE::EnvironmentCallFromUMode) {
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trap_frame.regs->sepc += 4;
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} else if (scause == RISCV64::CSR::SCAUSE::Breakpoint) {
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u32 break_instruction;
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if (!copy_from_user(&break_instruction, bit_cast<u32*>(trap_frame.regs->sepc), sizeof(break_instruction)).is_error()) {
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// Increment sepc based on the instruction length of the breakpoint instruction.
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if ((break_instruction & 0b11) == 0b11)
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trap_frame.regs->sepc += 4;
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else
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trap_frame.regs->sepc += 2;
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}
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}
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if ((to_underlying(scause) & RISCV64::CSR::SCAUSE_INTERRUPT_MASK) != 0) {
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// Interrupt
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Processor::current().enter_trap(trap_frame, true);
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if (scause == RISCV64::CSR::SCAUSE::SupervisorTimerInterrupt) {
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RISCV64::Timer::the().handle_interrupt(*trap_frame.regs);
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} else if (scause == RISCV64::CSR::SCAUSE::SupervisorExternalInterrupt) {
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for (auto& interrupt_controller : InterruptManagement::the().controllers()) {
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u8 pending_interrupt = 0;
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while ((pending_interrupt = interrupt_controller->pending_interrupt())) {
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auto* handler = s_interrupt_handlers[pending_interrupt];
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VERIFY(handler);
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handler->increment_call_count();
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handler->handle_interrupt(*trap_frame.regs);
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handler->eoi();
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}
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}
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} else {
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TODO_RISCV64();
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}
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Processor::current().exit_trap(trap_frame);
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} else {
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// Exception
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Processor::current().enter_trap(trap_frame, false);
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if (trap_frame.regs->sstatus.SPIE == 1)
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Processor::enable_interrupts();
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using enum RISCV64::CSR::SCAUSE;
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switch (scause) {
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case InstructionAddressMisaligned:
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case LoadAddressMisaligned:
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case StoreOrAMOAddressMisaligned:
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handle_crash(*trap_frame.regs, "Unaligned memory access", SIGBUS, false);
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break;
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case InstructionAccessFault:
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case LoadAccessFault:
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case StoreOrAMOAccessFault:
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handle_crash(*trap_frame.regs, "Memory access fault", SIGBUS, false);
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break;
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case IllegalInstrction:
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handle_crash(*trap_frame.regs, "Illegal instruction", SIGILL, false);
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break;
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case InstructionPageFault:
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case LoadPageFault:
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case StoreOrAMOPageFault: {
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// The privileged ISA theoretically allows stval to always be zero (in which case we would report a page fault in the zero page).
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// But all implementations capable of running general purpose operating systems should probably set this CSR,
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// as otherwise you can't handle page faults.
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// We simply require that Sstvala (see RISC-V Profiles) is supported, which means stval is always set to the faulting address on a page fault.
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PageFault fault { VirtualAddress(trap_frame.regs->stval) };
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if (scause == InstructionPageFault)
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fault.set_instruction_fetch(true);
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else if (scause == LoadPageFault)
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fault.set_access(PageFault::Access::Read);
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else if (scause == StoreOrAMOPageFault)
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fault.set_access(PageFault::Access::Write);
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// RISC-V doesn't tell you the reason why a page fault occurred, so we don't use PageFault::set_type() here.
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// The RISC-V implementation of Region::handle_fault() works without a correct PageFault::type().
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fault.handle(*trap_frame.regs);
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break;
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}
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case EnvironmentCallFromUMode:
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syscall_handler(&trap_frame);
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break;
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case Breakpoint:
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if (trap_frame.regs->previous_mode() == ExecutionMode::User) {
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auto* current_thread = Thread::current();
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auto& current_process = current_thread->process();
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if (auto* tracer = current_process.tracer())
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tracer->set_regs(*trap_frame.regs);
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current_thread->send_urgent_signal_to_self(SIGTRAP);
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} else {
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handle_crash(*trap_frame.regs, "Unexpected breakpoint trap", SIGTRAP, false);
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}
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break;
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default:
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VERIFY_NOT_REACHED();
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};
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Processor::disable_interrupts();
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Processor::current().exit_trap(trap_frame);
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}
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}
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// FIXME: Share the code below with Arch/x86_64/Interrupts.cpp
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// While refactoring, the interrupt handlers can also be moved into the InterruptManagement class.
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GenericInterruptHandler& get_interrupt_handler(u8)
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{
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TODO_RISCV64();
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}
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// Sets the reserved flag on `number_of_irqs` if it finds unused interrupt handler on
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// a contiguous range.
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ErrorOr<u8> reserve_interrupt_handlers(u8)
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{
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TODO_RISCV64();
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}
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static void revert_to_unused_handler(u8 interrupt_number)
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{
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auto* handler = new UnhandledInterruptHandler(interrupt_number);
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handler->register_interrupt_handler();
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}
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// FIXME: Share the code below with Arch/{x86_64,aarch64}/Interrupts.cpp
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void register_generic_interrupt_handler(u8 interrupt_number, GenericInterruptHandler& handler)
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{
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auto*& handler_slot = s_interrupt_handlers[interrupt_number];
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if (handler_slot == nullptr) {
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handler_slot = &handler;
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return;
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}
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if (handler_slot->type() == HandlerType::UnhandledInterruptHandler) {
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auto* unhandled_handler = static_cast<UnhandledInterruptHandler*>(handler_slot);
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unhandled_handler->unregister_interrupt_handler();
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delete unhandled_handler;
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handler_slot = &handler;
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return;
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}
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if (handler_slot->is_shared_handler()) {
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VERIFY(handler_slot->type() == HandlerType::SharedIRQHandler);
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static_cast<SharedIRQHandler*>(handler_slot)->register_handler(handler);
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return;
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}
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if (!handler_slot->is_shared_handler()) {
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if (handler_slot->type() == HandlerType::SpuriousInterruptHandler) {
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// FIXME: Add support for spurious interrupts on riscv64
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TODO_RISCV64();
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}
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VERIFY(handler_slot->type() == HandlerType::IRQHandler);
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auto& previous_handler = *handler_slot;
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handler_slot = nullptr;
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SharedIRQHandler::initialize(interrupt_number);
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VERIFY(handler_slot);
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static_cast<SharedIRQHandler*>(handler_slot)->register_handler(previous_handler);
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static_cast<SharedIRQHandler*>(handler_slot)->register_handler(handler);
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return;
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}
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VERIFY_NOT_REACHED();
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}
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// FIXME: Share the code below with Arch/{x86_64,aarch64}/Interrupts.cpp
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void unregister_generic_interrupt_handler(u8 interrupt_number, GenericInterruptHandler& handler)
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{
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auto*& handler_slot = s_interrupt_handlers[interrupt_number];
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VERIFY(handler_slot != nullptr);
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if (handler_slot->type() == HandlerType::UnhandledInterruptHandler)
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return;
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if (handler_slot->is_shared_handler()) {
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VERIFY(handler_slot->type() == HandlerType::SharedIRQHandler);
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auto* shared_handler = static_cast<SharedIRQHandler*>(handler_slot);
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shared_handler->unregister_handler(handler);
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if (shared_handler->sharing_devices_count() == 0) {
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handler_slot = nullptr;
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revert_to_unused_handler(interrupt_number);
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}
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return;
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}
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if (!handler_slot->is_shared_handler()) {
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VERIFY(handler_slot->type() == HandlerType::IRQHandler);
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handler_slot = nullptr;
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revert_to_unused_handler(interrupt_number);
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return;
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}
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}
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void initialize_interrupts()
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{
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for (size_t i = 0; i < s_interrupt_handlers.size(); ++i) {
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auto* handler = new UnhandledInterruptHandler(i);
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handler->register_interrupt_handler();
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}
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}
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}
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