Liav A d6318f2cc6 Kernel: Ensure that we receive IRQs in PIO mode when IOAPIC is enabled ...

The IOAPIC manual states that "Interrupt Mask-R/W. When this bit is 1,
the interrupt signal is masked. Edge-sensitive interrupts signaled on
a masked interrupt pin are ignored." - Therefore we have to ensure that
we disable interrupts globally with cli(), but also to ensure that we
invoke enable_irq() before sending the hardware command that generates
an IRQ almost immediately.

2020-04-15 16:40:16 +02:00

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